IEEE

FPGA-Based Implementation of Sobel Edge Detection Using Verilog HDL with ROM-Encoded Grayscale Input

Abstract: A hardware-enhanced Sobel edge detection algorithm on an FPGA with Verilog HDL is implemented in this paper. Grayscale image data is preprocessed with MATLAB and stored in ROM inside the ...
IEEE

A Configurable FPGA Accelerator for 2D Convolution with Reduced Memory Footprint using Patch-Based General Matrix-Matrix Multiplication

Abstract: Convolution is considered as the core operation in any Convolutional Neural Network (CNN) model. However, these operations are computationally intensive and have higher latency. This problem ...
CU Boulder News & Events

Augmenting Flume Experiment Data Using a Convolutional Neural Network to Track Wood in Flow

Large wood (LW; >10 cm in diameter and >1 m in length) within river corridors - including channels and adjacent floodplains - plays a key role in shaping hydraulic conditions, sediment deposition and ...