AZOM

Curved Shapes with Mask Wafer Co-Optimization

One of the main challenges in developing semiconductor chip technology is making electronic components smaller and more effective. This difficulty is most noticeable in lithography, which is the ...
Electronics Weekly

Imec develops die-to-wafer bond process with 2µm pad pitch

Imec has developed a Cu-to-Cu and SiCN-to-SiCN die-to-wafer bonding process resulting in a Cu bond pad pitch of only 2µm at <350nm die-to-wafer overlay error, achieving good electrical yield. Such ...
Semiconductor Engineering

Inspecting Unpatterned Wafers

Unpatterned wafer inspection, which has flown well under the radar for most of the semiconductor industry, is becoming more critical amid the need to find defects earlier in the manufacturing process ...
Semiconductor Engineering

Using Fab Sensors To Reduce Auto Defects

The semiconductor manufacturing ecosystem has begun collaborating on ways to effectively use wafer data to meet the stringent quality and reliability requirements for automotive ICs. Silicon ...
Business Wire

The New Stratus 200 and Stratus 300 Provides Highest Throughput Electrodeposition System with Maximum Wafer Yield

BILLERICA, Mass.--(BUSINESS WIRE)--July 10, 2006--NEXX Systems, a leading provider of processing equipment for advanced wafer level packaging applications, is pleased to introduce the Stratus 200 and ...
pv magazine International

Longi, ANU develop gettering-based process to improve n-type wafer quality

The Chinese module maker and the Australian National University utilized phosphorus diffusion gettering and another defect mitigation strategy to improve the quality of n-type wafers. The proposed ...