EDN

The war is over: C++ and SystemC coexist in a single flow

Since its debut in 2004, the current generation of high-level synthesis (HLS) tools has made tremendous progress in terms of both quality of results (QoR) and wider applicability. The success of this ...
Design-Reuse

From Behavioral to RTL Design Flow in SystemC

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...
Electronic Design

SystemC Advances Set the Stage For New SoC Design Flow Strategy

A new specification for Open Core Protocol (OCP) users will present a seamless flow for complex system-on-a-chip (SoC) designs. Publication of the spec comes via the OCP International Partnership (OCP ...
Semiconductor Engineering

Is SystemC Broken?

In order to perform architectural exploration, performance analysis and optimization, early validation of software, improved productivity in hardware development and many other tasks, the industry ...
EDN

Nine reasons to adopt SystemC ESL design

A SystemC-enabled electronic system-level (ESL) design and verification environment targets the design, analysis, optimization and verification of system-on-chip (SoC) platform models. Such an ...
Design-Reuse

Methodology for Rapid Development of Loosely Timed and Approximately Timed TLM Peripherals

This paper proposes a methodology to develop SystemC TLM 2.0 peripheral models and a technique to incorporate Loosely Timed (LT) and Approximately Timed (AT) modes in them. This methodology uses ...