Semiconductor Engineering

A Comparative Evaluation Of DRAM Bit-Line Spacer Integration Schemes

With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic as ...
Semiconductor Engineering

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of ...
EDN

DRAM basics and its quest for thermal stability by optimizing peripheral transistors

For decades, compute architectures have relied on dynamic random-access memory (DRAM) as their main memory, providing temporary storage from which processing units retrieve data and program code. The ...
TweakTown

Samsung's 1c DRAM yields leap: 0% to 40% giving the greenlight for HBM4 mass production

TL;DR: Samsung's 1c DRAM yield for next-gen HBM4 memory has improved from 0% to around 40%, enabling planned mass production later this year. Design restructuring and process optimizations enhanced ...