EDN

Design Guide for Sub-Clock Circuits

In this application note, we will discuss the design guides for sub-clock circuits. We will discuss some points on board design such as stabilizing oscillation and trace example as well as reference ...
EDN

Enhance circuit timing design with programmable clock generators (Part 1 of 2)

For additional ways to reduce EMI through board layout and related techniques, this 4-minute video gives tips and techniques: http://focus.ti.com/lit/ml/sllc324 ...
Electronic Design

Clock Generators Bring Stability to Timing-Circuit Designs

Clock speed is equivalent to data movement in applications that receive and process hundreds of megabytes of data each second. Applications involved in moving enormous volumes of data include cellular ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
Electronic Design

Introduction to Multisource Clock Tree Systems

Multisource CTS represents a new clock-distribution technology that fills the methodology gap between conventional CTS and pure clock mesh. Whereas pure clock mesh delivers the best possible clock ...
Hackaday

Building A Transistor Clock From Scrap

[Phil] has already built a few clocks with Nixies, VFDs, and LED matrices. When his son requested his own clock, he wanted to do something a little different. Inspired by the dead bug style of [Jim ...