For a useful primer on circuit design, see Optimize your DSPs for power and performance. To learn how power and performance vary with voltage and temperature, see Push performance and power beyond the ...

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and ...

Asynchronous processors, which function without a global clock, have emerged as a compelling alternative to traditional synchronous architectures. Their design relies on handshake protocols and local ...

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...

As system-on-chip (SoC) designs grow larger, designers must grapple with serious global timing problems, the effect of wire loading and timing delays and the performance hit associated with supporting ...

LONDON — Tiempo AS (Grenoble, France) has said it will demonstrate the first synthesis tool for asynchronous logic that operates from standard design languages at the Design Automation Conference, due ...

Given the growing importance and impact of portable, battery-operated devices in today’s society, it’s easy to understand why power consumption has become such a critical factor in IC design. But it’s ...