Aldec has said that it is now supplying the most comprehensive implementation of VHDL 2019 for both Windows and Linux platforms with the latest release of Riviera-PRO (release version 2021.04).
SAN JOSE, Calif. and HENDERSON, Nev., July 20, 2020 (GLOBE NEWSWIRE) -- SmartDV™ Technologies, the Proven and Trusted choice for Design and Verification Intellectual Property (IP), and Aldec today ...
HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., an industry leader in electronic design verification, has added VHDL-2018 interfaces and automatic coverage model generation to its Riviera-PRO™ advanced ...
Henderson, NV – January 23, 2012 – Aldec, Inc., announces the release of ALINT 2012.01,a design rule checking application for HDL-based FPGA/ASIC designs. The new release adds documentation ...
SAN MATEO, Calif.—EDA tool vendor Aldec Inc. is seeking a preliminary injunction in San Francisco's Federal Court to stop Xilinx Inc. from distributing Aldec's ActiveParts tools as part of Xilinx's ...
Aldec, Inc., a supplier of mixed-language simulation and advanced design tools for ASIC and FPGA devices, has announced support for the Open IP Encryption Initiative design flow in the latest version ...
Henderson, Nevada - December 27, 2004-- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera 2004.12. The new ...
Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has added an automatic UVM Generator function to Riviera-PRO. The addition is ...
HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
EDA firm Aldec has unveiled a hardware prototyping board for chip developers using intellectual property cores. The board uses FPGAs, and can take both Altera and Xilinx devices. IP and other design ...
San Francisco: EDA vendor Aldec Corporation has unveiled its new Register Transfer Level (RTL) and gate level simulator for FPGA design and verification engineers. The company says that the Active-HDL ...
Xilinx says Aldec lawsuit is baselessGale Morrison On the eve of Programmable World, a day long global simulcast from dozens of locations due to showcase Xilinx’ programmable logic technology and tier ...
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